2027 Graduate_Standard Cell Library

About PDG 部门介绍

Arm China PDG group design and support physical IP on Chinese foundry partners and offers IC designers a wide range of choices from its broad portfolio of Arm China owned physical IP. Arm China PDG group physical IP include high-performance, high-density, low-power and ultra-low power Logic IP, Embedded Memory Compiler and Interface IP for each foundry and process technology. These productions ease implementation challenges for advanced nodes to accelerate core hardening, speed SoC implementation and reduce project rise for IC design.

安谋科技 PDG（物理IP设计团队）致力于在中国本土晶圆厂合作伙伴的工艺上设计、开发并支持物理 IP，并凭借安谋科技自有的广泛物理 IP 产品组合，为客户提供丰富多样的选择。安谋科技 PDG 团队的物理 IP 产品涵盖了高性能、高密度、低功耗及超低功耗逻辑 IP、嵌入式存储器编译器（Embedded Memory Compiler）等。这些产品能够缓解先进工艺节点的设计实现挑战，从而加速内核硬化（Core Hardening）进程、提升 SoC 整体实现效率，并降低 IC 设计项目的整体风险。

Job Responsibility:

岗位职责：

1. Participate in the schematic design, physical layout design, and simulation verification of standard cell libraries.

参与标准单元库的电路设计（Schematic）、物理版图设计（Layout）及仿真验证工作；

2. Optimize the library's performance-power-area (PPA) metrics to meet design requirements across various process nodes.

优化标准单元库的性能、功耗与面积（PPA）指标，以满足不同工艺节点的设计要求；

3. Generate various library database views for standard cells, including GDS/CDL/LEF/NDM/LIB/DB/Verilog/ATPG/APLCHAR/PGV, etc.

生成标准单元库的多格式视图数据库，包括但不限于：GDS、CDL、LEF、NDM、LIB、DB、Verilog、ATPG、APLCHAR、PGV 等；

4. Library database views QA work to ensure database quality.

负责库视图数据库的 QA（质量保证）工作，确保交付的数据库质量；

5. Support standard library user guide documentation and maintenance.

支持标准单元库用户指南的编写与维护。

6. Proficiently use EDA tools (e.g., Cadence Virtuoso, Spectre, Innovus; Synopsys Primetime, ICC, Calibre) for library design, simulation, and verification.

熟练使用各类 EDA 工具（如 Cadence Virtuoso、Spectre、Innovus；Synopsys PrimeTime、ICC；以及 Calibre 等）进行库设计、仿真与验证；

7. Develop TCL/Perl/Python/Skill scripts to automate design flows and improve efficiency.

开发 TCL / Perl / Python / Skill 脚本，实现设计流程的自动化，提升工作效率。

Job Requirements:

任职要求:

1. Master's degree or above in Microelectronics, Integrated Circuit Design, Electronic Engineering, Computer Science, or related fields.

微电子、集成电路设计、电子工程、计算机科学或相关专业，硕士及以上学历；

2. Strong foundation in digital circuit design, familiarity with CMOS technology and semiconductor physics.

具备扎实的数字电路设计基础，熟悉 CMOS 工艺及半导体物理学；

3. Understanding of standard cell library design flows and basic concepts in timing analysis and power optimization.

了解标准单元库的设计流程，掌握时序分析与功耗优化的基本概念；

4. Familiarity with Linux operating systems; TCL/Perl/Python/Skill scripting skills are preferred.

熟悉 Linux 操作系统；具备 TCL / Perl / Python / Skill 等脚本编写能力者优先；

5. Prior experience with EDA tools (e.g., Cadence, Synopsys) for digital circuit design is a plus.

具备使用 EDA 工具（如 Cadence、Synopsys）进行数字电路设计经验者优先；

6. Experience with layout design tools (e.g., Virtuoso), circuit simulation (Spectre/HSPICE), or static timing analysis (e.g., PrimeTime) is a plus.

具备版图设计工具（如 Virtuoso）、电路仿真工具（如 Spectre/HSPICE）或静态时序分析工具（如 PrimeTime）实操经验者优先。

Job Location: Chengdu/Shanghai

工作地点: 成都/上海