Analog Layout Manager

Responsibilities:

Manage a layout team of approximately 10 engineers and have successfully delivered whole layout projects end-to-end

Lead and oversee IC layout design using the Cadence Virtuoso platform

Drive layout migration across technology nodes, leveraging Auto Placement and Auto Routing flows

Perform and maintain XL compliance checks to ensure clean and rule-compliant design databases

Collaborate with circuit design, process engineering, and CAD teams to ensure layout aligns with design intent

Support batch post-simulation flows including QRC, EMIR, and Quantus Insight

Review layout work and mentor junior engineers on best practices

Continuously improve layout productivity through automation and EDA tool optimization

Requirements:

8+ years of IC layout experience, with preference for analog/mixed-signal background

Proficient in Cadence Virtuoso XL and layout automation tools

Familiar with advanced technology nodes (Foundry 3–7nm, FinFET/CMOS)

Hands-on experience with QRC/EMIR extraction and post-layout simulation

Strong understanding of DRC, LVS, QRC, EMIR, EMX, PERC flows

Excellent cross-team collaboration skills with fluent English communication (spoken and written)