Staff/Principal DFT Engineer

Key job responsibilities

· Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes

· Define and execute DFT strategies across scan insertion and ATPG, memory BIST, logic BIST, and analog/PHY test considerations, optimizing coverage, quality, and costs within subsystems and across the entire design

· Develop, maintain, and continuously optimize DFT-related flows, ensuring high-quality DFT implementation from RTL through silicon bring-up

· Collaborate closely with cross-functional teams to ensure testability is designed in from architecture all the way through signoff

· Mentor and develop junior engineers through code reviews, DFT methodology training, and technical guidance on scan insertion, ATPG, and BIST practices

PREFERRED QUALIFICATIONS

· M.Sc. or above in Microelectronics, Integrated Circuit Design, Electrical Engineering, or related fields

· 8+ years of hands-on DFT experience

· Experience in creating and implementing chip-level DFT architecture

· Experience with industry-standard DFT tools and practices, including ATPG, JTAG, and MBIST, as well as trade-offs between test quality and test time

· Excellent problem-solving, debug, root-cause analysis, and communication skills

· Experience in building and developing high-quality DFT methodology/flows

· Good exposure to cross-functional areas including RTL & clock design, STA constraints development and analysis for DFT modes

· Practical experience with ATE/silicon debug