SoC Design Verification Engineer

Responsibilities:

Take on the tasks of IP/Subsystem/SoC-level verification

Analyzing and decomposing SoC/Subsystem architecture, microarchitecture, and functional test points

Defining verification strategies, detailed test plans, and methodologies

Develop, integrate, and debug verification environments for SoC/Subsystem/IP

Create and optimize test cases to achieve functional and code coverage targets

Analyze complex SoC/Subsystem user cases and corner cases, implementing targeted verification solutions

Participate in full-chip verification flow (RTL-to-GLS), including low-power and performance verification.

Work closely with architect, design, and SW teams to ensure verification completeness

Requirements:

The candidate is preferred to be MSEE with minimum of 5+ years, in digital ASIC/SOC design verification. More experience will be considered as staff engineer or lead.

Familiar with one of major verification languages: UVM, C, C++, SystemVerilog

Good knowledge of design verification methodology, such as UVM or OVM and coverage driven verification methodology

Strong knowledge of AMBA protocols (AXI/ACE/APB/AHB)

Proficiency with EDA tools(Xrun/VCS/Indago/Verdi, etc.)

Be familiar with scripting language, such as Python, Perl, C shell, Makefile etc.

Strong analytical, and problem solving skills.

Background in one of the areas below will be a strong plus:

PCIe Gen3+, DDR/HBM, NoC

Ethernet, USB, UFS, SD/SDIO/eMMC

Video/Display/ISP pipeline verification

NPU/GPU/GPGPU verification

C/C++ development, simulation modeling (co-sim/emulation)

Tape-out experience(mass production chips preferred)

Our Culture

We act with Belief—embracing uncertainty, owning challenges and driving solutions. With Solidarity, we align closely and back each other up. Staying Down-to-Earth, we drive efficiency, address customers’ real pain points and accelerate delivery. Fueled by Passion, we aim high, stay sharp, and never stop improving.