Staff/Principal Backend Design Engineer

Staff/Principal Backend Design Engineer

Introduction

We are seeking a Staff/Principal Backend Design Engineer to join our ASIC service team. In this role, you will be responsible for the end-to-end physical implementation of ARM architecture-based server CPUs.

Responsibilities

• Manage the daily operations and make technical decisions for the backend design team, lead the team to deliver high-quality results on time, and ensure chip PPA targets are achieved.

• Define the overall chip-level physical implementation strategy, including top-level floorplan, block partition, timing constraint development, and power budget allocation.

• Lead the development of backend design methodologies for advanced process nodes, establish design rules and process standards and drive their implementation, and continuously optimize toolchains and design flows.

• Develop backend implementation plans for each die in multi-die/Chiplet architectures and drive cross-die co-design, ensuring the correctness and reliability of inter-die interface physical design.

• Oversee the quality of the entire backend design flow, covering synthesis, PR/CTS/STA,

• Engage with EDA vendors and IP providers for technical alignment, evaluate IP physical delivery quality, and drive vendors to resolve technical issues.

• Lead the development of automation scripts and process optimization for backend design, continuously improving overall team efficiency and design quality.

Basic Qualifications

• M.Sc. or above in Microelectronics, Integrated Circuit Design, Electrical Engineering, or related fields.

• 8+ years of IC backend/physical design experience.

• Mastery of full-flow physical design for advanced process nodes, with proven track record of complete delivery from RTL synthesis to GDSII tape out.

• Proficiency in mainstream backend design tools: Fusion Compiler/Innovus for place and route, PrimeTime/Tempus for static timing analysis.

• Familiarity with top-level floorplan and modular implementation strategies for large-scale SoC chips.

• Knowledge of low-power physical design methodologies including multi-voltage domains, multi-clock domains, and Power Gating.

Stand Out Qualifications

• Experience with ARM CPU Core backend integration and optimization.

• Experience building backend design automation platforms or toolchains.

• Experience with backend design for server CPUs or high-performance computing (HPC) chips.

• Familiarity with advanced packaging technologies (2.5D/3D) and chip-package co-design processes.