SOC Architecture Expert

SOC Architecture Expert

Introduction

We are seeking a SOC Architect to join ASIC service team. In this role, you will deeply participate in the architecture design and front-end implementation of ARM-based high-performance server CPU SOC chips.

Responsibilities

• Deeply participate in the architecture design of next-gen server CPUs. Lead and finalize the detailed design specifications for the SOC, ensuring alignment with product requirements and technical feasibility.

• Take ownership of the end-to-end front-end design process, including subsystem architecture, RTL design, clock/reset architecture, low-power design (UPF), SDC constraint definition, SOC integration, and synthesis.

• Lead the evaluation of performance, power, and area for modules and subsystems. Formulate and execute targeted optimization strategies based on design requirements and process technology characteristics to meet PPA targets.

• Drive module-level and system-level verification efforts to ensure logical correctness. Collaborate closely with backend teams during physical design iterations to resolve timing bottlenecks, perform power analysis, and ensure design-for-test (DFT) readiness.

Basic Qualifications

• B.Sc./M.Sc./Ph.D. in Computer Architecture, Microelectronics, Electrical Engineering, or related fields.

• Proven experience in complete SoC design flows and successful tapeouts. Experience with advanced process nodes (7nm and below) is highly preferred.

• Deep understanding of high-performance server chip design requirements and technical pain points.

• Expert knowledge of mainstream bus protocols (CHI, ACE, AXI4/5, AHB, APB) and experience in protocol-based subsystem design and integration.

• Strong grasp of PPA optimization techniques and hands-on experience in resolving complex design issues independently.

• Proficient in front-end design tools and flows: Lint/Spyglass, CDC analysis, Synthesis, STA, and Physical Design (PR) flows.

Stand Out Qualifications

• Experience integrating complex IPs such as ARM CPU cores, CMN (Coherent Mesh Network), GIC, MMU, DDR, PCIe, CXL, and UCIe.

• Experience in designing AI accelerators, NOC (Network-on-Chip), GPU/NPU subsystems, or low-power island architectures.

• Prior experience in mass production of high-performance ARM server CPUs or other complex chips using advanced process nodes.

• Experience with high-bandwidth, low-latency server chip design and large-scale parallel computing architectures.