Staff/Principal SIPI Engineer

Staff/Principal SIPI Engineer

Introduction

We are seeking a Staff/Principal Signal and Power Integrity (SIPI) Engineer to join our ASIC service team. In this role, you will be responsible for end-to-end SIPI work from design to mass production, establish technical standards, and ensure our chips achieve industry-leading performance and reliability under advanced process nodes and packaging technologies.

Responsibilities

• Own end-to-end signal integrity (SI) and power integrity (PI) analysis and optimization across chip, package, and PCB levels for ARM server CPU products.

• Lead chip-package-PCB co-simulation and co-optimization for high-speed interfaces (SerDes, PCIe, DDR, Ethernet, UCIe) and power distribution networks (PDN), resolving cross-level complex SIPI issues.

• Develop and maintain company-level SIPI design specifications, guidelines, best practices, and sign-off criteria to ensure SIPI quality across all products.

• Establish and standardize SIPI simulation workflows and automation platforms, developing automation scripts using Python/Matlab to improve overall team efficiency.

• Provide technical leadership and mentorship to the team, review engineers' design plans and simulation results, and foster the development of team members.

• Drive cross-functional SIPI issue resolution and clearly communicate technical risks, mitigation measures, and progress plans to project and executive stakeholders.

• Participate in key technical decisions and promote the implementation of SIPI solutions for cutting-edge technologies such as 2.5D/3D packaging and Chiplet interconnections.

Basic Qualifications

• M.Sc./Ph.D. in Microelectronics, Electromagnetic Field and Microwave Technology, Electrical Engineering, Communication Engineering, or related fields.

• 5-10+ years of progressive high-speed SI/PI analysis experience, with a proven track record of delivering complete SIPI solutions for production silicon.

• Solid understanding of electromagnetic field theory, microwave transmission line principles, and proficiency in both time-domain and frequency-domain analysis methods.

• Familiar with industry-standard SI/PI simulation tools: Ansys HFSS, Cadence Sigrity (SIwave/PowerSI), Keysight ADS, or Mentor HyperLynx.

• In-depth knowledge of mainstream high-speed interface protocols (SerDes, PCIe Gen5/6, DDR5/6, Ethernet, UCIe) and their SIPI requirements.

• Hands-on experience with post-silicon high-speed interface bring-up and SIPI characterization for production chips.

• Proficiency in developing complex automated simulation workflows and data post-processing tools using Python/Matlab.

• Excellent cross-functional communication and leadership skills, with the ability to influence technical decisions and drive rapid problem resolution.

Stand Out Qualifications

• Experience with multi-die/Chiplet architectures and inter-die interconnect SIPI analysis.

• Experience with SIPI analysis for advanced 3D packaging technologies (2.5D/3D TSV, CoWoS, HBM3/HBM4 integration).

• Extensive post-silicon SIPI debugging and characterization experience, proficient in using oscilloscopes, vector network analyzers (VNA), and time domain reflectometers (TDR).

• Experience with full-link PDN co-optimization across chip, package, and PCB.

• Familiarity with the characteristics and challenges of domestic semiconductor processes and packaging technologies.

Our Culture

We act with Belief—embracing uncertainty, owning challenges and driving solutions. With Solidarity, we align closely and back each other up. Staying Down-to-Earth, we drive efficiency, address customers’ real pain points and accelerate delivery. Fueled by Passion, we aim high, stay sharp, and never stop improving.