Layout Engineer

PDG introduction:

Arm china PDG group design and support physical IP on Chinese foundry partners, and offers IC designers a wide range of choices from its broad portfolio of arm china owned physical IP. Arm china PDG group physical IP include high-performance, high-density, low-power and ultra-low power Logic IP, Embedded Memory Compiler and Interface IP for each foundry and process technology. These productions ease implementation challenges for advanced nodes to accelerate core hardening, speed SoC implementation and reduce project rise for IC design.

Job Description:

Responsible for the development of physical IP layouts in advance CMOS and FinFET process.

Perform physical verification(DRC/LVS/Antenna) for standard cell, memory, and IO, from bottom cells to top hierarchy.

Capable of developing workflow automation for Memory compiler layout design.

Undertake the assignments or in a team.

Work closely with circuit design engineers to ensure highest quality physical IP layout.

Education and Qualification:

Bachelor degree in related fields such electrical engineering, computer science, physics and etc.

Should have good understanding of basic CMOS, FinFET and SOI process and circuits.

Experience or familiarly in various physical verification checks, like DRC, LVS, ERC, Antenna,Density, ESD, LUP, IREM, etc.

Familiar with layout design and verification tools(virtuoso, Laker, Calibre).

Familiar with process design principle and place and route effect.

Familiar with script language, such as Perl, Python, TCL.

Good communication skills, learning competency, self-motivated and team spirit.