Sr. CPLD Engineer

在捷普，我们打造品牌，打造世界——这也就是为什么我们会成为技术上最领先和最可信赖的制造解决方案提供商。不管我们服务的对象是全世界最大最知名的品牌还是最新潮的技术初创公司，我们的决心永远不会动摇。我们与这些品牌的愿景是相一致的，那就是：打造一个更好的、更安全的、更干净的地球。

At Jabil (NYSE: JBL), we are proud to be a trusted partner for the world's top brands, offering comprehensive engineering, supply chain, and manufacturing solutions. With 60 years of experience across industries and a vast network of over 100 sites worldwide, Jabil combines global reach with local expertise to deliver both scalable and customized solutions. Our commitment extends beyond business success as we strive to build sustainable processes that minimize environmental impact and foster vibrant and diverse communities around the globe.

JOB SUMMARY

Under the guidance of management, develop new engineering designs of basic to moderate complexity. Gather design requirements and recommend implementation steps for basic to moderate reference designs, including modifications to existing products. Perform and analyze circuit designs of basic to moderate complexity, escalating more complex issues to management or senior team members. Develop subsystem architecture under the direction of a Lead Engineer or above.

ESSENTIAL DUTIES AND RESPONSIBILITIES

Work closely with Hardware, BIOS, BMC, and Firmware teams for CPLD / FPGA design, validation, and maintenance.

Develop Server / Storage production power on sequence control logic by CPLD / FPGA.

Implement new technology and design concept in CPLD / FPGA.

Design test plan, development specifications, and issue tracking.

JOB QUALIFICATIONS

KNOWLEDGE REQUIREMENTS

TECHNICAL KNOWLEDGE & SKILLS

5+ years of working experience in CPLD / FPGA development.

Familiar with CPLD / FPGA design and Verilog/VHDL coding.

Experience in I2C, SPI, UART, and SGPIO protocols.

Experience in RTL coding and simulation.

Building in CPLDs and FPGAs, including coding practice, RTL coding standards, using Git, building test benches, etc.

Familiar with System Verilog, Git, server product, and UVM is a plus.

NON-TECHNICAL KNOWLEDGE & SKILLS

Influence others and share best practices.

Effectively communicate with a good understanding of English.

Work as part of a global team.

EDUCATION & EXPERIENCE REQUIREMENTS

Electrical Engineering Degree (BSEE/MSEE or equivalent experience)

5+ years of experience in CPLD / FPGA design or another key competency.

Or an equivalent combination of education, training, or experience.

Domestic and international travel is required (within 1 month)

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捷普，包括其子公司，是一个就业机会均等的雇主，在考虑候选人是否符合雇佣标准时，种族、肤色、宗教信仰、国籍、性别、性取向、性别认同、性别、年龄、残疾、遗传、退伍军人身份和其他所有受法律保护的特征均不会被考虑在内。

Accessibility Accommodation

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