SoC整合專案副理/專案經理

工作項目：
1. SOC integrator!
A challenging job for integrating the designs from over 100 digital designers and tens of analog designers.
A challenging job of using deep submicron process.
2. Building & Improving the standard environment for digital designers to run front-end flow, such as synthesis, STA analysis, linting, and so on.
3. Cooperating with APR designers for backend timing closure.
4. Block / Whole-Chip CTS (Clock-tree Synthesis) analysis and improvement.

應徵條件：
1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程等相關科系畢業為主。
2. 熟悉 verilog, verdi, STA, synthesis.
3. 具 CTS(Clock tree synthesis) Design/Debug經驗者尤佳。
4. 會寫 script如 perl者更佳。
5. 具六年以上相關工作經驗。