锦鲤求职岗位描述
Key qualifications:
1. Master degree or above with EE or CS background
2. Familiar with SystemVerilog and Verilog
3. Exposure to OVM/UVM/VMM methodology
4. Exposure to constrained-random based verification environment
5. Exposure to create coverage model and drive coverage closure in including code/functional coverage.
6. Be able to develop a test bench from scratch
Preferred qualifications:
1. Familiar with PCI/USB/SATA/Serdes
2. Familiar with Bluetooth
3. Familiar with SOC bus fabric and AXI/AHB/OCP bus protocols
4. Familiar DDR2/3/4
5. Familiar with any type of flash memory
6. Familiar SVA
7. Familiar Formal verification methodology
8. Experience of writing bootloader for ARM/MIPS CPUs
9. Perl/Python experience
Job descriptions:
1. Test plan creation
2. Develop testbench, test cases, reference model, coverage model and regression suite
3. Run RTL and gate level simulation, debug failures, manage bug tracking
4. Drive and achieve coverage closure
(MD17C0031)