SoC實體設計工程師C1

工作項目：
1. Physical implementation.
2. Hierarchical floorplan.
3. Auto Place&Route.
4. Clock tree synthesis.
5. signal integrity analysis.
6. static timing analysis.
7. dynamic power analysis.
8. physical verification.
9. APR flow development.

應徵條件：
1. 碩士以上; 電機工程、電子工程、資訊工程、資訊科學相關科系畢業為主。
2. 熟悉 Synopsys EDA tool, Cadence EDA tool, Mentor Graphic tool, C/C++/perl/tcl.
3. 熟悉 SunOS, Solaris, Windows.
4. 無經驗可，惟具 EDA tool development, IC Physical implementation, IC digital design and APR相關經驗者尤佳。