Digital chip verification engineer

Responsibilities：

1. Responsible for sorting out verification documents and optimizing verification system;

2. Responsible for module-level subsystem and chip-level functional verification;

3. Responsible for post-imitation environment construction and post-imitation.

Qualifications：

1. A required master degree or above in microelectronics, electronics, computer or other related majors;

2. Have a rigorous and clear logical thinking ability, have the keen attention to details, have the ability to focus on a problem for a long time, have the ability to find and solve problems independently;

3. Proficient in verilog and system verilog languages, have verification experience;

4. Proficient in C language;

5. Being familiar with scripts such as perl, UVM verification methods are preferred;

6. Familiar with VCS, NCVERILOG and other related EDA tool